An array of memory cells, such as dynamic random access memory (DRAM) cells, non-volatile memory cells, non-volatile storage devices or static random access memory (SRAM) cells or content addressable memory (CAM) cells, is a well-known mechanism used in various computer or processor based devices to store digital bits of data. The various computer and processor based devices may include computer systems, smartphone devices, consumer electronic products, televisions, internet switches and routers and the like. The array of memory cells are typically packaged in an integrated circuit or may be packaged within an integrated circuit that also has a processing device within the integrated circuit. The different types of typical memory cells have different capabilities and characteristics that distinguish each type of memory cell. For example, DRAM cells take longer to access, lose their data contents unless periodically refreshed, but are relatively cheap to manufacture due to the simple structure of each DRAM cell. SRAM cells, on the other hand, have faster access times, do not lose their data content unless power is removed from the SRAM cell and are relatively more expensive since each SRAM cell is more complicated than a DRAM cell. CAM cells have a unique function of being able to address content easily within the cells and are more expensive to manufacture since each CAM cell requires more circuitry to achieve the content addressing functionality.
Various computation devices that may be used to perform computations on digital, binary data are also well-known. The computation devices may include a microprocessor, a CPU, a microcontroller and the like. These computation devices are typically manufactured on an integrated circuit, but may also be manufactured on an integrated circuit that also has some amount of memory integrated onto the integrated circuit. In these known integrated circuits with a computation device and memory, the computation device performs the computation of the digital binary data bits while the memory is used to store various digital binary data including, for example, the instructions being executed by the computation device and the data being operated on by the computation device.
More recently, devices have been introduced that use memory arrays or storage cells to perform computation operations. In some of these devices, a processor array to perform computations may be formed from memory cells. These devices may be known as in-memory computational devices.
Big data operations are data processing operations in which a large amount of data must be processed. Machine learning uses artificial intelligence algorithms to analyze data and typically require a lot of data to perform. The big data operations and machine learning also are typically very computationally intensive applications that often encounter input/output issues due to a bandwidth bottleneck between the computational device and the memory that stores the data. The above in-memory computational devices may be used, for example, for these big data operations and machine learning applications since the in-memory computational devices perform the computations within the memory thereby eliminating the bandwidth bottleneck.
The in-memory computational devices typically use well known standard SRAM or DRAM or CAM memory cells that may perform computations. For example, a standard 6T SRAM cell that can be used for computation is shown in FIG. 1. The standard 6T SRAM cell may have a bit line (BL) and a complementary bit line (BLb) and a word line (WL) that are connected to the cell. The cell may include two access transistors (M13, M14) and each access transistor has a source coupled to the bit lines (BL and BLb), respectively. Each access transistor also has a gate and the gate of both access transistors is connected to the word line (WL) as shown in FIG. 1. The drain of each access transistor may be connected to a pair of inverters (I11, I12) that are cross coupled to each other. One side of the cross coupled inverters nearest the bit line BL may be labeled D and the other side of the cross coupled inverters nearest the complementary bit line (BLb) may be labeled Db. The cross-coupled inverters acts as a storage element of the SRAM cell as is known in the art and the reading/writing of data to/from the SRAM cell is known in the art and is now described in more detail.
When two cells connected to the same bit line are turned on, the bit line (BL) can perform an AND function of the two bits of data stored in the cells. During a read cycle, both BL and BLb have a static pull up transistor, and if the data in both of the cells is logic high “1”, then the BL stays as 1. If any or both of the data in the cells is/are logic low “0”, then the BL is pulled to a lower level and will be a logic 0. By sensing the BL level, an AND function is performed using the 2 cells. Similarly, if 3 cells are turned on, the BL value is a result of an AND function of data stored in the 3 cells. During a writing operation, multiple word lines (WL) can be turned on, so multiple cells can be written at the same time. In addition, the write can be done selectively, or Selective Write, meaning no write will be performed if both BL and BLb are held high during the write cycle.
The cell shown in FIG. 1 has its drawbacks. On a read cycle, when multiple cells are turned on, if all but one cell stores a low logic value of “0”, then the BL voltage level is a ratio of the pull down transistors of the “0” cell against the BL pull up transistor. If the BL voltage level is too low, then it will cause the cell storing a logic “1” to flip to logic “0”. As a result, it would seem desirable to have a strong BL pull up transistor to allow more cells to be turned on. However, if only 1 cell contains “0” data during reading, a strong BL pull up transistor make the “0” signal small so that the data is difficult to sense.
On a write cycle, the cell in FIG. 1 also has drawbacks. If multiple cells into which data is to be written are active, the BL driver for writing needs to strong enough to flip the driver of each memory cell's latch devices, I11 and I12 shown in FIG. 1. Furthermore, the more WLs that are turned on in the write cycle, the stronger the write driver needs to be which is undesirable.
On a Selective Write cycle, the cell in FIG. 1 also has drawbacks. In particular, the BL pull up transistor needs to be strong to fight against the “0” stored in the multiple active cells. Similar to the read cycle above, when all but one cell is active and contains a “0”, then the lone cell containing a “1” is susceptible to the instability caused by the lower BL level.
Thus, it is desirable to have a SRAM cell that may be used for computation that does not have drawbacks of the typical 6T SRAM cell shown in FIG. 1.